Virage Logic to Focus on 90nm Yield and Cost Management at Design Automation Conference

FREMONT, Calif., May 26 /PRNewswire-FirstCall/ -- Virage Logic , a leading provider of best-in-class semiconductor IP platforms, will share its experiences and insights on 90 nanometer (nm) design and its inherent yield and cost challenges at this year's Design Automation Conference (DAC), to be held June 7 - 11 at the San Diego Convention Center.

In addition to in-depth presentations in its booth (#2941) and suites, Virage Logic will be co-hosting two key panel programs, one with TSMC and another with IBM and Chartered Semiconductor. Following is more detail on topics and panelists. For panel registration information, meeting requests, or to find out specific information on other Virage Logic DAC activities, visit the Virage Logic DAC online registration Web page: http://www.gelfuzion.com/virage/asp/index.asp .

  TSMC & Virage Logic Breakfast Panel Session

  Managing the Rising Design Costs of SoCs

This lively discussion will feature a broad range of executive-level perspectives from key stakeholders in the system-on-chip (SoC) supply chain. Co-hosted by TSMC and Virage Logic, the panelists will include: Chris Hamlin, LSI Logic; Dr. Edmund Cheng, Synopsys; James Wang, TSMC; and Adam Kablanian, Virage Logic. The panel will be moderated by EE Times Editor-in-Chief Brian Fuller. This event will be held Wednesday, June 9th, from 7:30 - 9:30 a.m., at the San Diego Convention Center, Upper Level (3rd Floor), Meeting Room 31B & 31C.

  IBM, Chartered Semiconductor and Virage Logic Lunch Panel

  The Brave New World of Nanometer Design

Virage Logic has assembled a knowledgeable panel of experts who will discuss the future of designing and manufacturing chips in the Nano Age. Co-hosted by IBM, Chartered Semiconductor and Virage Logic, the panelists will include: Jonathan Fields, Agere Systems; Mike Kerbaugh, IBM; Dr. John Martin, Chartered Semiconductor Manufacturing; and Dr. Alex Shubat, Virage Logic. The panel will be moderated by EE Times Editor Ron Wilson. This event will be held Wednesday, June 9th, from 11:30 a.m. - 1:00 p.m., at the San Diego Convention Center, Upper Level (3rd Floor), Meeting Room 31B & 31C.

Virage Logic will also be presenting in a number of its VIP Partner booths and suites.

  -- Synopsys Strategic Alliances Partner Suite
     Virage Logic's comprehensive semiconductor IP offering for Synopsys'
     Galaxy Platform will be featured on Wednesday, June 9th, 4:00 - 5:00
     p.m. in the Synopsys Booth (#4825).

  -- Synopsys Interoperability Breakfast (Sponsored by IBM)
     Myth Busters | Interoperability: Languages and Libraries
     The Virage Logic Area, Speed and Power (ASAP) Logic(TM) Metal
     Programmable and Standard Cell Libraries will be highlighted at this
     event scheduled for Wednesday, June 9th, from 7:30 - 10:00 a.m., at the
     San Diego Marriott Hotel.

  -- Virage Logic IBM Booth Presentation
     Virage Logic will highlight how its Technology-Optimized Platforms and
     ASAP Logic Metal Programmable Cell Libraries - available on the jointly
     developed Chartered Semiconductor and IBM 90nm manufacturing process --
     help SoC designers meet the challenges of 90nm design. The presentation
     will be on Tuesday, June 8th at 2:00 p.m. in the IBM Booth
    (#3726/3914).

  -- Virage Logic UMC Booth Presentation
     Virage Logic's presentation in UMC's Booth (#3934) will explain the
     benefits of a highly differentiated, silicon-proven semiconductor IP
     platform offering.  Presentations will be given on Monday, June 7th at
     1:30 p.m.; Wednesday, June 9th at 3:00 p.m.; and Thursday, June 10th at
     10:15 a.m.

  Virage Logic Suites -- Online Meeting Registration Now Open

Virage Logic will offer a number of in-depth product and technology presentations in its suites. Interested parties may log on to the Virage Logic Web site to book a private meeting. To register online, go to: http://www.gelfuzion.com/virage/asp/index.asp .

For more information or to register for DAC, please go to: http://www.dac.com/41st/reg.html .

About Virage Logic

Virage Logic Corp. (NASDAQ: VIRL) is a leading provider of best-in-class semiconductor IP platforms based on memory, logic, and I/Os that are silicon- proven and production ready. Virage Logic meets market demands for cost reduction, while improving performance and reliability for fabless and integrated device manufacturer (IDM) companies focused on the consumer, communications and networking, handheld and portable, and computer and graphics markets. Virage Logic is headquartered in Fremont, California and has sales, support and engineering offices worldwide. For more information, visit http://www.viragelogic.com/ or call 877-360-6690 toll free or 510-360-8000.

Safe Harbor Statement under the Private Securities Litigation Reform Act of 1995:

Statements made in this news release, other than statements of historical fact, are forward-looking statements, including, for example, statements relating to trends, business outlook, products, and customer relationships. Forward-looking statements are subject to a number of known and unknown risks and uncertainties, which might cause actual results to differ materially from those expressed or implied by such statements. These risks and uncertainties include Virage Logic's ability to forecast its business, including its revenue, income and order flow outlook; Virage Logic's ability to execute on its strategy to become a provider of semiconductor IP platforms; Virage Logic's ability to continue to develop new products and maintain and develop new relationships with third-party foundries and integrated device manufacturers; adoption of Virage Logic's technologies by semiconductor companies and increases or fluctuations in the demand for their products; the company's ability to overcome the challenges associated with establishing licensing relationships with semiconductor companies; the company's ability to obtain royalty revenues from customers in addition to license fees, to receive accurate information necessary for calculating royalty revenues and to collect royalty revenues from customers; business and economic conditions generally and in the semiconductor industry in particular; competition in the market for semiconductor IP platforms; and other risks including those described in the company's Annual Report on Form 10-K for the period ended September 30, 2003, and in Virage Logic's other periodic reports filed with the SEC, all of which are available from Virage Logic's website (http://www.viragelogic.com/) or from the SEC's website (http://www.sec.gov/), and in news releases and other communications. Virage Logic disclaims any intention or duty to update any forward-looking statements made in this news release.

All trademarks are the property of their respective owners and are protected herein.

CONTACT: Sabina Burns of Virage Logic Corp., +1-510-743-8115, or
sabina.burns@viragelogic.com; or Kerry McClenahan of McClenahan Bruer
Communications, +1-503-546-1002, or kerry@mcbru.com, for Virage Logic Corp.

Web site: http://www.viragelogic.com/